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Lattice Semiconductor
Functional Description
Signal Descriptions
The I/O port definitions are given in Table 2-2 . The optional ports are represented as portname and may be
selected based on the parameters given in Table 3-1 on page 18.
Table 2-2. Interface Signal Descriptions
Name
Bits
Active
I/O
Description
All Configurations
clk
rstn
din
1
1
1 to 32
?
L
—
I
I
I
System Clock. This is the reference clock for input and output data.
Asynchronous System Reset.
Input Data in Signed Format.
Output Data in Signed Format.The width of this port is equal to the next higher inte-
ger value of [ Input data width + Stages (log 2 (RATE x DF_DELAY)], where,
dout
2 to 160
—
O
? RATE = Rate when Programmable rate is not selected. ?
RATE = Max rate when Programmable rate is selected.
? DF_DELAY = Delay when Programmable delay is not selected. ?
DF_DELAY = Max delay when Programmable delay is selected.
outvalid
inpvalid
1
1
H
H
O
I
Output Data Valid. Indicates that output port dout contains a valid sample.
Input Data Valid. Indicates that the input port din contains a valid sample.
Ready For Input. Indicates that the CIC filter is ready to accept an input sample in the
rfi
1
H
O
next clock cycle. If rfi is low, the input sample in the next clock cycle will be ignored
even if inpvalid is asserted high. Available only if Filter type = “Interpolator”.
Multi-channel Mode Only (when Number of channels > 1)
ibstart
obstart
1
1
H
H
I
O
Input Block Start. Indicates that the first valid data of an input data cycle is being pre-
sented at the input port din .
Output Block Start. Indicates that output port dout contains a valid sample for the
first channel.
IPUG42_02.6, August 2010
12
Cascaded Integrator-Comb (CIC) Filter User’s Guide
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